第十一週碩博專討演講(4/27)
2023.04.24
演講者：曾偉志 博士
美國Intern
題目：Scaling down and stacking up: how the trends in
semiconductors are affecting chemical-mechanical planarization (CMP).
內容摘要：
Over the past 5+ decades, the semiconductor industry has been following the Moore’s law, which perceives that roughly every 2 years, the number of transistors on microchips will double, while the cost of computers is halved. The law itself has been driving the advancement of industry to achieve increased speed and capability with lower cost of ownership.
Consequently, semiconductors are scaling down and stacking up at the same time: device feature size is shrinking in the x-y plane, while even more layers of materials are being processed in the z- direction. Such aggressive geometric driving force engenders a multitude of challenges to process technologies like CMP. First, it increases the number of CMP steps inevitably; second, it calls for the necessity of CMP for new materials (e.g., new work function metals for gates, new barrier/liner for Cu interconnects) to meet the required specifications; and thrid, the tolerance for non-uniformity, variabiity, and defectivity become even more stringent than ever.
In general, the 3 main CMP performance metrics, planarity, uniformity, and defectivity are being stretched to meet the specs down to nm scale on one hand, while still required to polish 3D stacks on the order of mm on the other. Such critical challenges call for innovations in HW/SW such as more robust end-point, APC/AI-based control…etc.; in consumables such as higher slurry selectivity, higher pad planarzation efficiency in varying length scales, and more effective cleaning chemistry..etc. In this contribution, the CMP challenges and potential solutions in the era of aggressive semiconductror scaleing and stacking will be reviewed and projected.
時間： 2023/04/27 (Thu) 3:10 PM
地點：成功校區三系館鋼構區(3F)共同教室 A1302演講廳
美國Intern
題目：Scaling down and stacking up: how the trends in
semiconductors are affecting chemical-mechanical planarization (CMP).
內容摘要：
Over the past 5+ decades, the semiconductor industry has been following the Moore’s law, which perceives that roughly every 2 years, the number of transistors on microchips will double, while the cost of computers is halved. The law itself has been driving the advancement of industry to achieve increased speed and capability with lower cost of ownership.
Consequently, semiconductors are scaling down and stacking up at the same time: device feature size is shrinking in the x-y plane, while even more layers of materials are being processed in the z- direction. Such aggressive geometric driving force engenders a multitude of challenges to process technologies like CMP. First, it increases the number of CMP steps inevitably; second, it calls for the necessity of CMP for new materials (e.g., new work function metals for gates, new barrier/liner for Cu interconnects) to meet the required specifications; and thrid, the tolerance for non-uniformity, variabiity, and defectivity become even more stringent than ever.
In general, the 3 main CMP performance metrics, planarity, uniformity, and defectivity are being stretched to meet the specs down to nm scale on one hand, while still required to polish 3D stacks on the order of mm on the other. Such critical challenges call for innovations in HW/SW such as more robust end-point, APC/AI-based control…etc.; in consumables such as higher slurry selectivity, higher pad planarzation efficiency in varying length scales, and more effective cleaning chemistry..etc. In this contribution, the CMP challenges and potential solutions in the era of aggressive semiconductror scaleing and stacking will be reviewed and projected.
時間： 2023/04/27 (Thu) 3:10 PM
地點：成功校區三系館鋼構區(3F)共同教室 A1302演講廳